The present invention relates to a method for producing a resist structure on a semiconductor material which has an opening tapering towards the semiconductor material.
With respect to semiconductor components there is an ever increasing need to apply a metallization to the surface of a semiconductor layer structure, whereby the contact area between the semiconductor material and the metal is optimally small, while at the same time, an optimally great amount of metal should be applied so as to reduce the lead resistance. These types of metallizations, for example, are required in the manufacture of field effect transistors for operation in ultra-high frequency ranges. Felt or T-gates, as they are referred to in the industry, are produced in order to be able to provide extremely small gate lengths, particularly in the sub- .mu.m range, with a metallization which has an optimally large cross-section. The felt or T-gates are produced by vapor-depositing a mushroom-shaped resist structure with metal. However, in this process, there is a problem of structuring a resist layer with the required profile.
A typical method for structuring the resist on the semiconductor material is by successively applying a sequence of resist layers. In this process, each layer is individually exposed and developed. A disadvantage of this method is that it requires a technically involved sequence of exposure steps which need to be adjusted relative to the other steps. The difficulties which result from having to make all these adjustments can be avoided by applying a sequence of resist layers that have different sensitivities. These layers are then exposed and developed simultaneously. The mushroom-shaped structure of the opening results because the upper, more sensitive layers are increasingly over-exposed. However, the desired short length of the contacting surface (below 0.5 .mu.m), does not occur because the structure of the resist layers is so thick. When the semiconductor layer structure does not have a planar surface, it is impossible to apply the first resist so that it has a sufficient thinness. The first method described above is not usable in cases where there is a non-planar semiconductor layer structure.